1. Field of the Invention
The present invention relates to a nonvolatile storage device and a self-redundancy method of using the same.
2. Description of the Related Art
As is known, redundancy structures are provided for replacing failed memory locations so as to prevent the rejection of the entire storage device if one location of the memory array fails.
Normally, the replacement of the failed memory location with the redundancy part takes place in final production steps, when a special test, referred to as electrical wafer sorting (EWS), detects a failure.
The structure commonly used for storing the addresses of redunded or replaced memory locations is principally made up of CAM banks, i.e., nonvolatile storage units, programmable and erasable by the manufacturer in the testing step. In particular, when a failure is detected in a memory location, information designed to determine uniquely the memory location to be replaced is stored in the CAMs.
The information stored in the CAMs may be of various kinds: the addresses of the location to be repaired, whether and which bit packet of the word addressed is to be replaced, whether an entire sector is to be replaced, whether the bank has already been used for storing an address of a failed location or not (guard information), etc.
The number of banks present in the redundancy structure defines the maximum number of packets (columns, bytes, rows, sectors—hereinafter indicated also as memory units or memory locations) that can be replaced in the entire memory array. When, then, the location has been replaced, it is necessary to carry out a number of operations for identifying the redundancy location that stores the information instead of the failed location.
The check and the possible redundancy replacement are carried out for any operation, either reading or writing, that is to be performed on the failed location, when addressing of the location in the memory array is required.
The structure for managing redundancy has the function of verifying whether the memory array location addressed is among the replaced ones and, if so, provides for activation of the redundancy locations and for the simultaneous de-activation of the decoding of the memory array corresponding to the defective location.
In particular, the address of the location that is to be read or written (program or erase) is compared with the addresses of the replaced locations during the testing steps and, in the event of coincidence with one of them, a “hit” signal is generated that has the task of activating the redundancy circuitry and of replacing the failed location (whether it be a bit, a byte, a word, or a sector) by physically pointing to the redundancy unit.
In the ensuing description, the discussion will be an example of sector redundancy. The following considerations are, however, readily applicable to other types of redundancy, such as, for example, column redundancy, row redundancy, etc.
In the literature, sector redundancy is complementary to column redundancy and is preferred to row redundancy for high memory density devices (i.e., with a density greater than or equal to 16 Mbits). Furthermore, sector redundancy is preferred as regards area, speed and performance of the memory during reading operations, and finally because of a greater flexibility in solving serious problems that may arise in the array, such as for example shorts between wordlines and substrate.
At present, the common sector redundancy envisages a plurality of redundancy units, which, for area efficiency and yield, may be expressed as a redundancy unit (a redundancy sector) for each multiple of 16 Mbits. Each redundancy unit is therefore associated to a CAM comprising a plurality of nonvolatile cells, equal to the number of bits of the address necessary for identifying each sector of the memory array. Each CAM thus identifies a failed sector.
Furthermore, a further nonvolatile memory element, referred to as guard CAM, is associated to each redundancy unit and stores a guard information specifying whether the associated redundancy unit has been used or not.
During reading or programming of cells of the memory array, the comparison between the addresses supplied from outside by the user and the ones stored in the CAMs generates, in the presence of the guard information activated, the “hit” signal mentioned above.
In present memory architectures, the content of the CAMs, programmed, as has been said, during the EWS testing step, is read continuously throughout the lifetime of the device, using a structure the cells whereof are directly connected, through the drain terminal, to latches that buffer the content of the information present in the CAMs.
Programming is performed by using the same switch structure (the so-called “program loads”) present in the array, disabling the array-decoding circuits, enabling the redundancy ones, and causing the datum (drain voltage) to move along bitlines (main bitline in the case of a hierarchical architecture) present in the memory array.
This architecture does not enable ease of activation and management of redundancy for addressing the nonvolatile cells during normal operation of the device by using an automatic replacement algorithm that exploits structures and circuits already present in the device.